A tunnel oxide layer is a layer of high quality oxide which insulates a gate of a semiconductor device, such as a floating gate, from an underlying silicon substrate. A tunnel oxide layer may, for example, be used in a semiconductor memory device, such as a non-volatile memory.
One of the challenges of improving non-volatile memories is improving the data retention characteristics of the memories without having to change the core logic devices in such a way that high speed logic performance is compromised. Optimizing the properties of the tunnel oxide layer is a way to optimize the retention characteristics of the memory.
U.S. Pat. No. 7,115,469 describes a process for fabrication of a semiconductor device including an ONO structure as a component of a flash memory device. U.S. Pat. No. 7,071,538 describes a semiconductor device including a substrate that further includes source, drain and channel regions. US 2005/0090062 describes a method for forming a nitrided tunnel oxide layer.